1. Field
Various embodiments described herein relate generally to delay line architectures including two or more delay line modules. Each delay line module may include semiconductor switches to direct a signal on a thru, non-delayed path, and a delayed path. The semiconductor switches may include various semiconductors including metal-oxide semiconductor field effect transistors (MOSFET), metal-semiconductor field effect transistors (MESFET), bipolar junction transistors (BJT), P-N diodes, PIN diodes, and other semiconductor constructs. In an embodiment, the semiconductor switches may be fabricated on silicon-on-insulator (“SOT”) and silicon-on-sapphire (“SOS”) substrates, although other fabrication technologies, such as bulk-silicon and micro-electro-mechanical systems (MEMS) technologies may also be used in other embodiments. Delay line modules may further include embedded attenuators.
2. Description of Related Art
Delay line architectures including multiple delay line modules may experience performance degradation due to linear phase shifts caused by voltage standing wave reflections (VSWR) between the delay line modules. It may be desirable to improve delay line architecture linear phase accuracy by reducing VSWR in the architecture; the present invention provides system, apparatus, and methods for same.